Conventionally, a switching regulator provides a UVLO circuit which stops operations of a control circuit for preventing an error in the operations when a power source voltage becomes, a value less than a predetermined value (for example, refer to Patent Document 1).
FIG. 10 is a circuit diagram showing a conventional boost type switching regulator having a UVLO circuit.
In a switching regulator 100 shown in FIG. 10, a power source voltage Vcc is raised to be a predetermined voltage and the raised voltage is output as an output voltage Vout from an output terminal OUT, and PWM (pulse width modulation) control is applied to control an on-duty cycle of a switching transistor M101 so that a divided voltage Vfb formed by dividing the output voltage Vout becomes a reference voltage Vref.
An overcurrent detecting circuit 108 detects an overcurrent output from the output terminal Vout by using a current flowing into the switching transistor M101. When the overcurrent detecting circuit 108 detects the overcurrent, a delay circuit 109 outputs a high level signal after a predetermined delay period has passed, and stops a voltage boost operation by switching off the switching transistor M101 via a NOR circuit 101.
In addition, a UVLO circuit 110 monitors the power source voltage Vcc, and outputs a low voltage detection signal UVLOa of a high level when the power source voltage Vcc is lowered to a value less than a predetermined value. Further, the UVLO circuit 110 causes the switching transistor M101 to enter a cut-off status by switching off the switching transistor M101, initializes a soft-start circuit 107 so that the soft-start circuit 107 can execute a soft start operation when the voltage boost operation restarts, and causes the delay circuit 109 to reset a delay timer which counts the delay period so that the counting number of the delay timer becomes a predetermined initial value.
In addition, a switching regulator control circuit is disclosed (for example, refer to Patent Document 2). The switching regulator control circuit provides a first UVLO circuit and a second UVLO circuit whose detection voltages are different from each other for controlling operations of an output buffer circuit. The structure and purpose of the present invention are different from those in Patent Document 2.
[Patent Document 1] Japanese Laid-Open Patent Application No. 2006-115594
[Patent Document 2] Japanese Laid-Open Patent Application No. 2005-078557
However, in FIG. 10, in a case where an overcurrent is generated due to some reason and a signal showing generation of the overcurrent is output from the overcurrent detecting circuit 108 to the delay circuit 109, after the delay timer of the delay circuit 109 starts to count the delay period, when the power source voltage Vcc is lowered and the UVLO circuit 110 outputs the low voltage detection signal UVLOa of the high level, the delay circuit 109 resets the counting number of the delay timer to be the initial value.
After this, when the power source voltage Vcc is raised, the UVLO circuit 110 makes the low voltage detection signal UVLOa a low level, and if for some reason the overcurrent problem is not solved, the overcurrent detecting circuit 108 detects the overcurrent and the above operations are repeated. Since the switching transistor M101 is normally controlled to be in an on or off status until the delay timer of the delay circuit 109 completes counting the predetermined period, an overcurrent preventing operation is not executed even if the switching regulator 100 has the overcurrent detecting circuit 108 and the delay circuit 109.